The development of integrated circuits has been characterized by the ever increasing number of devices placed on a single semiconductor substrate. In order to achieve higher device density, smaller geometry devices have been developed. Predictably, a number of structural and operational problems arise when conventional lower density designs and processes are scaled down in an attempt to achieve the desired device size. Two such problems in small geometry MOS devices are so-called short channel effects and the relatively high resistivity of silicon.
The problem of short channel effects is created, in part, by electrical interference between the MOS gate field and the doped source and drain regions. The interference can lead to electron tunneling between source, drain and gate regions. One solution to reduce short channel effects is to create lightly doped drain/source (LDD) regions on the side of the drain and source regions, respectively, proximate the gate location. Electrical interference from the gate field is thereby lowered reducing electron tunneling. U.S. Pat. Nos. 4,701,423 and 4,703,551 discuss in greater detail short channel effects and the use of LDD regions.
The relatively high resistance of silicon is a problem because both the doped single crystal silicon source and drain regions and polysilicon gate region carry current. The relatively high resistance of silicon is generally not a problem with large scale integrated circuits due to the relatively large cross section for carrying current. However, with very large scale integrated circuits the current carrying cross section is reduced thereby increasing the effective device resistance. Increased sheet resistance affects device performance by slowing down device response time. One solution to this problem is to provide a metal silicide layer, such as titanium silicide, on top of the silicon source and drain regions and the polysilicon gate.
In the past, the formation of titanium silicide has been achieved by a three step process. First, a layer of titanium silicide is deposited over the entire semiconductor structure including silicon and oxide regions and the structure is subjected to a low temperature anneal in the presence of nitrogen. This creates a layer of titanium silicide overlying the silicon regions and a layer of titanium nitride overlying the entire structure. Second, the titanium nitride and any nonreacted titanium is removed by means of a selective chemical etch thereby preventing the titanium nitride or nonreacted titanium from conductively interconnecting the titanium silicide on the electrode regions. Third, the device is subjected to a high temperature anneal to stabilize the titanium silicide and reduce the titanium silicide resistance to its final value.
The resulting titanium silicide is self-aligned with respect to the underlying silicon electrode regions. What is meant by "self-aligned" is that there is no masking step required to align the titanium silicide with the silicon electrode regions. The chemical reaction forms titanium silicide only where the titanium overlies exposed silicon.
The cost of producing a semiconductor device bears a proportional relationship to the number of processing steps required to form the device. Moreover, each additional processing step has the potential for introducing impurities and/or for adversely affecting the integrity of previously formed device structure. Thus, the reduction of processing steps is highly desirable, particularly if it can be achieved without affecting the quality of the device.